Title:
【発明の名称】半導体メモリ装置
Document Type and Number:
Japanese Patent JPH079944
Kind Code:
B2
Abstract:
PURPOSE:To eliminate the leakage of charges to a substrate and a malfunction resulting from alpha-rays, to enable correct operation by increasing the quantity of charges stored and to lengthen a memory holding time by forming three layers constituting a capacitor cell. CONSTITUTION:A groove 2 is dug to a P type semiconductor substrate 1, and a P<+> diffusion layer 10 is shaped onto the inner surface of the groove. An insulating layer 4 consisting of SiO2 on the inside of the diffusion layer 10 and a polysilicon layer 11 on the inside of the layer 4 are formed. An insulating layer 4 on the inside of the layer 11 and a polysilicon layer 12 on the inside of the layer 4 are shaped. An N channel MOS transistor 6 for taking in and out charges to and from the capacitor cell is formed. According to the constitution, a capacitor element is connected in parallel, thus doubling the quantity of charges stored. Charges are stored in the layer 11 through the transistor 6, thus resulting in no leakage to the substrate 1, then preventing the effect of electrons generated in the substrate 1 by alpha-rays.
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Inventors:
Yukimasa Uchida
Kimura Toru
Kimura Toru
Application Number:
JP15970484A
Publication Date:
February 01, 1995
Filing Date:
July 30, 1984
Export Citation:
Assignee:
Toshiba Corporation
Toshiba Microelectronics Co., Ltd.
Toshiba Microelectronics Co., Ltd.
International Classes:
G11C11/401; H01L21/822; H01L21/8242; H01L27/04; H01L27/10; H01L27/108; (IPC1-7): H01L21/8242; H01L21/822; H01L27/04; H01L27/108
Domestic Patent References:
| JP583260A | ||||
| JP58213460A | ||||
| JP53108392A |
Attorney, Agent or Firm:
Kazuo Sato (2 outside)
Next Patent: プレス金型の位置出し機構