Title:
【発明の名称】多目的誤り訂正計算回路
Document Type and Number:
Japanese Patent JPH10508441
Kind Code:
A
Abstract:
A bit-oriented error correction calculation circuit performs numerous mathematical operations including bit-oriented convolutions, inversions, multiplications, additions, and bi-directional basis conversions. The circuit includes three banks of registers (400,401,402) connected as a convolution circuit to produce a sequence of inner products with respect to the first bank of registers (400) and the second bank of registers (401). Each of the banks of registers (400,401) has a bank loading switch (440,441,442) connected to a serial input terminal thereof for loading a selected one of a plurality of serial multibit values into the banks, including selective gating of feedback signals from respective feedback circuits (450,452) in registers (400,402) and (inter alia) constant values. The values of the feedback multipliers are selectively changeable in accordance with a field length of the value involved in error correction of data. Further included are a summation circuit (320); a comparison circuit (360); and a bi-directional conversion unit for converting an m-bit input value from an input basis representation to an output basis representation.
Inventors:
Zouk, Christopher Pee.
Application Number:
JP51042196A
Publication Date:
August 18, 1998
Filing Date:
September 15, 1995
Export Citation:
Assignee:
Cirrus Logic, Incorporated
International Classes:
G06F7/00; G06F7/535; G06F7/72; G06F7/52; G06F7/76; G06F11/10; G06F17/10; G11B20/10; G11B20/18; H03M13/00; H03M13/15; H03M13/35; H03M13/37; (IPC1-7): H03M13/00; G06F11/10; G11B20/18
Attorney, Agent or Firm:
Shusaku Yamamoto