Title:
【発明の名称】メモリ素子内の欠陥セルに対処する回路、システム、および方法
Document Type and Number:
Japanese Patent JPH11501435
Kind Code:
A
Abstract:
A data processing system 100 is provided which includes a memory 104, an array 204 of memory cells arranged in rows and columns, each row being addressable by an address. Address generation circuitry 201/202 is provided for generating ones of the addresses for accessing selected ones of the rows in the array 204. An associative memory 203 is coupled to the address generation circuitry 201/202 for translating a first address, received from the address generation circuitry 201/202 and addressing a defective one of the rows of the array 204, into a second address addressing an operative one of the rows in array 204, the second address being sent to the memory.
Inventors:
Cross, Randolph A.
Application Number:
JP51614096A
Publication Date:
February 02, 1999
Filing Date:
November 06, 1995
Export Citation:
Assignee:
Shirasu Logic, Inc.
International Classes:
G09G5/00; G11C29/00; G11C29/04; G11C29/24; (IPC1-7): G11C29/00; G09G5/00
Attorney, Agent or Firm:
Akira Asamura (3 outside)