Title:
【発明の名称】クラスタ・コンピュータ・システムにおけるアドレス変換
Document Type and Number:
Japanese Patent JPH11512857
Kind Code:
A
Abstract:
In order to achieve the integration of a plurality of processors, each capable of directly addressing a limited internal space storage range, with a larger external memory space (e.g., a mass memory), the processors are organized into clusters, each having a plurality of processors and a common secondary cache. Each cluster is assigned a two-bit cluster number. Intermediate a primary cache in each processor and the secondary cache in the cluster, an address translator is provided for effecting transformation between internal memory space addresses and external memory space addresses. The external memory space is divided into areas private to each cluster and shared by all the processors. An internal address indicator bit, in conjunction with the cluster number from a requesting processor primary cache, is employed to set up the transformation either to the private external space of that cluster or the shared external space. In the reverse external-to-internal transformation, a pair of indicator bits are employed to set up the generation of an internal address and an indicator that the external address defines either shared external space or private external space for the designated cluster. A cluster member number assigned to each processor is used by the secondary cache of each cluster to track which processor sends/receives information to/from the mass memory.
Inventors:
Russell W. Guensner
Robins, Renato
Robins, Renato
Application Number:
JP51446197A
Publication Date:
November 02, 1999
Filing Date:
October 04, 1996
Export Citation:
Assignee:
Blu-HN Information Systems Incorporated
International Classes:
G06F9/46; G06F12/02; G06F12/06; G06F12/08; G06F15/16; (IPC1-7): G06F12/02; G06F9/46; G06F12/06; G06F15/16
Attorney, Agent or Firm:
Kazuo Shamoto (4 outside)