Document Type and Number:
Japanese Patent JPS4956506
Kind Code:
A
Abstract:
1389551 Data transmission; error correction DEFENCE SECRETARY OF STATE FOR 6 July 1973 [15 May 1972] 22705/72 Heading H4P Multiplex digital telecommunications apparatus comprises facilities for encoding and decoding digital signals according to any selected one of a set of predetermined block codes having different rates and different errorcorrecting capabilities. The block codes are of the form (nkt) where n is the total number of digits in a block, k is the number of data digits and t is the number of errors corrected. Examples are given of (11, 7, 1); (11, 4, 2); and 11, 1, 5) codes. The encoder Fig. 1 (not shown) includes a buffer store (1) arranged to receive binary data in blocks of k digits and to apply the k digits of each block to a set of r parity check encoder circuits (3). Another store (5) receives the outputs from the first store and also those from the encoder circuits. The decoder, Fig. 2, includes: a buffer store 10, for providing on separate lines simultaneously, representations of digital signals belonging to received blocks of signals; a set of syndrome-element deriving circuits 13 comprising modulo-two adders arranged for simultaneously deriving all the syndrome elements; a set of error-detecting circuits 14 for simultaneously deriving error indications of any information digit and comprising coincidence gates; and correcting gates 15 comprising modulo-two adders for providing corrected representations of the data signals.
Application Number:
JP5268973A
Publication Date:
June 01, 1974
Filing Date:
May 14, 1973
Export Citation:
International Classes:
H03M13/00; H04L1/00; G06F11/10; (IPC1-7): H04L1/10