Document Type and Number:
Japanese Patent JPS5087286
Kind Code:
A
Abstract:
1470441 Charge coupled devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 18 March 1974 [3 Dec 1973] 11973/74 Addition to 1470191 Heading H1K In operating a CCD as described in Specification 1470191 in which a layer of one conductivity type through which majority charge carrier packets are transferred is isolated from the surroundings in operation, has a doping and thickness such that it can be depleted throughout its thickness by an electric field without breakdown occurring, and comprises one or more surface adjacent regions beneath the transfer electrode system of higher doping than the rest of the layer, charge transfer efficiency is improved by adding a constant background quantity of majority carriers to each charge packet representing information to be transferred before the charge packets are transferred to the readout location. The background charge may constitute 10-50% of the maximum charge capable of being held at each storage site. Particularly when the device is used as an image sensor the background carriers may be provided by uniformly illuminating by an auxiliary radiation source prior to, during and/ of after the light integrating period. Pressure or heat may alternatively be used to generate the signal and/or background carriers. In all cases the background carriers may be introduced (as in Fig. 3) via a heavily doped input diffusion 102 within the N+ region of the layer 2 in which charge transfer occurs by impressing oppositely phased clock voltages on adjacent pairs of electrodes, the electrodes in each pair being relatively biased as shown to provide the asymmetrical potential wells needed to ensure unidirectional charge transfer. In operation the entire layer is initially depleted by suitably biasing the P type substrate 20. A shown the adjustable voltage source 111 supplies background charge, on which input signal source 110 superimposes charge representing information and this is gated to the first transfer electrode 4 by signals applied to gating electrode by a separate pulse source 115 or by clock line 24. In alternative forms in which a constant or pulsating voltage is applied to electrode 101, the input and background voltage signals are applied to the input gate 112, to the second of two serially arranged input gates to the first of which clock voltage is supplied, or to first and second gates respectively. All the embodiments of the aforementioned UK application may be modified for operation in the manner described above.
Application Number:
JP3339374A
Publication Date:
July 14, 1975
Filing Date:
March 25, 1974
Export Citation:
International Classes:
H04N5/335; G11C27/04; H01L21/339; H01L27/148; H01L29/10; H01L29/762; H01L29/768; (IPC1-7): G11C11/40; G11C19/28; H01L29/76; H01L31/14; H04N5/00