Document Type and Number:
Japanese Patent JPS5096106
Kind Code:
A
Abstract:
A pair of data stores are provided for each incoming multiplex line to a time division switch and successive frames of incoming data are alternately written into the stores using recovered line timing. The data is alternately read out of the stores and read out is generally phase shifted with respect to write in such that the write in to one store occurs simultaneously with the read out from the other. The recovered line timing used to write the data stores for a given line is not synchronized to the office timing used to read these stores and consequently more or less information can be written into the stores than is read out of them. To deal with this problem, a "slip" control circuit is used to compare the read and write cycles and when the read cycle effectively drifts or shifts to a predetermined extent in either direction relative to the write cycle, the control circuit operates on the read cycle to discard a frame of data or to double-read a frame of data, depending on the relative direction of drift between the read and write cycles.
Application Number:
JP14634974A
Publication Date:
July 31, 1975
Filing Date:
December 21, 1974
Export Citation:
International Classes:
H04J3/06; H04Q11/04; (IPC1-7): H04Q11/04