Document Type and Number:
Japanese Patent JPS5416384
Kind Code:
B2
Abstract:
A data processing system in which the operating logic thereof is arranged to provide for an overlapping of the access, or "fetch" operations such that access to a second memory module can be obtained by a processor unit before a data transfer has been completed with respect to a first memory module and read-out of the second memory module can process during the rewrite cycle of the first module to reduce the overall processing time. Such operation is made even more effective by arranging the system to utilize memory interleaving techniques. Further, the system of the invention can provide for multiprocessor operation with a single memory system by the use of appropriate time-sharing techniques wherein processors can be operated in time-phased pairs, suitable multiprocessor control logic being arranged to provide for preselected priority allocations among the multiple processors to permit the most effective management of the multiprocessor system.
More Like This:
Application Number:
JP11594675A
Publication Date:
June 21, 1979
Filing Date:
September 25, 1975
Export Citation:
International Classes:
G06F9/46; G06F12/06; G06F13/18; G06F15/16; G06F15/177