Document Type and Number:
Japanese Patent JPS5426189
Kind Code:
B2
Abstract:
An improved electronic sampling circuit combines the merits of a high-efficiency sampling system with the DC stability of the more standard feedback sampling system. The stabilized high-efficiency sampling system is very useful for sampling high-speed events at a fixed repetition rate, such as occurs in time-domain reflectometry applications, as well as for sampling at very low trigger rates or at varying trigger rates such as are found in general-purpose sampling equipment. The high-efficiency characteristic of this sampling system is obtained by adjusting the effective memory capacitance of a sampling gate to provide unity dot response. The DC stability characteristic is maintained by a resistive feedback loop from the system output to input.
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Application Number:
JP556274A
Publication Date:
September 03, 1979
Filing Date:
January 08, 1974
Export Citation:
International Classes:
G01R13/34; G11C27/02; H03K7/02