Document Type and Number:
Japanese Patent JPS5435052
Kind Code:
B1
Abstract:
A dynamic MOS memory array timing system. If a mode signal is at a first ("automatic mode") level, a refresh pulse is generated during every cycle defined by the system clock; if the mode signal is at a second ("fast mode") level, a refresh pulse is generated only when a refresh input to the timing system is energized. Where speed is not of the utmost importance, the system can be operated in the automatic mode and there is no need to provide externally controlled refresh input signals. On the other hand, where speed is important, each system cycle can be speeded up by generating refresh signals only periodically; the increased speed is gained at the expense of the additional control circuits required to generate the refresh input signals. Thus the same timing system can be used in many different applications. The timing system utilizes delay elements for generating the many pulses necessary during each cycle. The delay elements are tapped so that fewer separate elements are required. To prevent loading of the delay elements, high-input impedance ECL circuits are used in the timing system. However, to make the system compatible with TTL inputs and outputs, various TTL-ECL and ECL-TTL converter circuits are used throughout the system.
Application Number:
JP6333071A
Publication Date:
October 31, 1979
Filing Date:
August 19, 1971
Export Citation:
International Classes:
G11C11/406; G11C11/4067; G11C11/4076; H03K19/018; (IPC1-7): G11C11/34