Title:
TREATMENT OF SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPS58102528
Kind Code:
A
Abstract:
PURPOSE:To fabricate wafers having capability of gettering impurity element such as heavy metal within the inside and having the perfect mirror surface not allowing any contamination source on the surface by executing heat processing to semiconductor wafers, forming high density minor defects within wafers and eliminating a little amount of surface of the non-defect layer after forming said non-defect layer on the surface. CONSTITUTION:A CZ silicon wafer 11 is heat-treated in the non-oxidizing ambient in order to externally diffuse supersaturated oxygen 12. Next, heat treatment is carried out again in order to form the precipitation nucleus 13 of oxygen 12. At this time, a contamination source 14 is generated at the surface and it is eliminated by the next process. The wafer 11 thus fabricated has a defect nucleus 13 within it and is an ideal wafer having the perfect mirror surface. When the wafer 11 is placed into the element forming process, a minor defect 15 is generated within the wafer by the heat processing during the element forming processing. Thereby, the wafer provides the gettering effect and the perfect mirror surface.
Inventors:
MATSUSHITA YOSHIAKI
TAKASU SHINICHIROU
OGINO MASANOBU
WATANABE MASAHARU
HIRATSUKA HACHIROU
TAKASU SHINICHIROU
OGINO MASANOBU
WATANABE MASAHARU
HIRATSUKA HACHIROU
Application Number:
JP20109781A
Publication Date:
June 18, 1983
Filing Date:
December 14, 1981
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/306; H01L21/322; (IPC1-7): H01L21/306
Attorney, Agent or Firm:
Takehiko Suzue
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