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Title:
HIGH WITHSTAND VOLTAGE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS58135666
Kind Code:
A
Abstract:

PURPOSE: To easily obtain a high withstand semiconductor IC, by using an N type high impurity density diffused layer reaching a high density N type impurity buried layer as a channel stopper diffused layer.

CONSTITUTION: A cut 10 is provided at a part of an N type high impurity layer (N+ collector punched diffused layer) 9 reaching an N type high density impurity layer (N+ collector buried layer) 2 so as to surrounded an emitter region 5 and a base region 4, and emitter and base wirings 8' and 8 are provided via an insulation film 7 so as to pass over the cut 10. The gap between the collector electrode 11 and the wiring 8 on the side close thereto is set at a larger value either of a discharge gap or more determined by the maximum voltage of the circuit or the minimum value obtained in a photo resist process, and the N type high density impurity region 9 is not allowed to come under the wirings 8 and 8'.


Inventors:
IMAIZUMI ICHIROU
KIMURA MASATOSHI
OCHI SHIKAYUKI
Application Number:
JP472583A
Publication Date:
August 12, 1983
Filing Date:
January 14, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/768; H01L21/331; H01L23/522; H01L29/08; H01L29/41; H01L29/73; (IPC1-7): H01L21/88; H01L29/06; H01L29/44
Attorney, Agent or Firm:
Junnosuke Nakamura



 
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