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Patent Searching and Data


Title:
COMBINED EMITTER FOLLOWER CIRCUIT
Document Type and Number:
Japanese Patent JPS58168311
Kind Code:
A
Abstract:

PURPOSE: To eliminate the potential difference between input and output terminals, by correcting the difference of polarity between transistors TRs by a current mirror circuit which is provided between the input-side TR and the output- side TR.

CONSTITUTION: The collector current flowed to a PNP TR12 is flowed to a current mirror circuit consisting of a diode-connected PNP TR15 and an NPN TR 18. Since the emitter of an NPN TR16 operating as an emitter follower in the output side is connected to the NPN TR18, currents flowed to TRs 12 and 16 for no-signal are equal to each other approximately. The difference between currents flowed to both TRs is the difference of polarity. As the result, since the voltage between the base and the emitter of the TR16 and the voltage between the base and the emitter of the TR12 are equal to each other, the potential difference between input and output terminals is cancelled.


Inventors:
TANAKA MINORU
YAMADA HISASHI
Application Number:
JP5020882A
Publication Date:
October 04, 1983
Filing Date:
March 30, 1982
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03F3/50; H03F3/34; (IPC1-7): H03F3/50
Attorney, Agent or Firm:
Noriyuki Noriyuki