PURPOSE: To obtain a small-sized, high-speed semiconductor storage device by composing a write and a read register each of two data transfer means and two data latch means, and packaging those two registers on the same chip with a random access memory circuit.

CONSTITUTION: The write register has two transfer means, i.e. the 1st means 42 and the 3rd means 44 and two data latch means, i.e. the 2nd means 43 and the 4th means 45 and its input part is connected to an external data input terminal. The random access memory circuit 47 has a data input buffer and a data output buffer and the data input buffer is connected to the output of the write register. The read register has two data transfer means, i.e. the 5th means 50 and the 7th means 52 and two data latch means, i.e. the 6th means 51 and the 8th means 53. This storage device includes said registers and circuit. Consequently, parallel data are read and written independently.