Title:
ANALOG-TO-DIGITAL CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JPS5842317
Kind Code:
A
Abstract:
PURPOSE: To obtain a circuit for ease of circuit integration, by delaying a data strobe signal corresponding to an input, detecting the coincidence of delay of said signal, and counting a clock pulse corresponding to the delayed time.
CONSTITUTION: A data strobe signal A is applied to one input terminal In1 of a coincidence circuit 11 via a transistor (TR)T1 and also to another input terminal In2 directly. A capacitor C1 constitutes a delay means with the TRT1. The delay in the signal A is detected at the circuit 11 and the output signal C is applied to a logical circuit 12 together with a clock pulse signal . An output D of this logical circuit 12 is applied to a counter 13, where count is performed to obtain a digital signal output.
Inventors:
IWAMURA ATSUSHI
Application Number:
JP14077781A
Publication Date:
March 11, 1983
Filing Date:
September 07, 1981
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03M1/50; H03M1/00; H03M1/12; (IPC1-7): H03K13/20
Domestic Patent References:
| JPS558144A | 1980-01-21 | |||
| JPS5376079A | 1978-07-06 |
Attorney, Agent or Firm:
Takehiko Suzue