Title:
【発明の名称】オプトエレクトロニク半導体デバイス
Document Type and Number:
Japanese Patent JPS58501395
Kind Code:
A
Abstract:
An improved solid state relay and regulator having reduced turn-off time, analog or digital input, and analog or digital output, is obtained by using a depletion JFET as a variable resistance discharge path for a gate of a power MOSFET switching device wherein the gate is charged by a first set of photovoltaic cells optically coupled to but electrically isolated from an LED input. A second set of photovoltaic cells responsive to the same or a separate LED input hold the JFET in an Off state while the MOSFET gate is energized. Variable output and AND logic are obtained.
Inventors:
Fitps, Jiyoung Pee
Application Number:
JP50260282A
Publication Date:
August 18, 1983
Filing Date:
July 15, 1982
Export Citation:
Assignee:
Motro-La Inco-Polled
International Classes:
H01L31/12; H01H35/00; H03K17/687; H03K17/78; H03K17/785; (IPC1-7): H01H35/00; H01L31/12
Domestic Patent References:
| JPS5530292A | 1980-03-04 | |||
| JPS551732A | 1980-01-08 |
Attorney, Agent or Firm:
Kugoro Tamamushi