Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JPS6056311
Kind Code:
B2
Abstract:
A cell for a semiconductor memory of the static type employs only one conventional MOS transistor, along with a field implanted resistance and a vertical P-channel junction-type field effect transistor. These elements, along with a resistor element which may be another field implanted resistance or a polysilicon implanted resistance, provide a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.
Inventors:
DEBITSUDO JEI MATSUKUERUROI
Application Number:
JP231278A
Publication Date:
December 09, 1985
Filing Date:
January 12, 1978
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G11C11/41; G11C11/39; G11C11/412; H01L21/822; H01L21/8244; H01L27/04; H01L27/10; H01L27/11; H03K3/356; (IPC1-7): H01L27/10; G11C11/40; H01L27/04; H01L29/80
Attorney, Agent or Firm:
Asamura Akira