Document Type and Number:
Japanese Patent JPS6135587
Kind Code:
B2
Abstract:
CPU - I/O BUS INTERFACE FOR A DATA PROCESSING SYSTEM There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or interfacing means for interfacing with I/O means(bus structure). The I/O means includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/ controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology.
Inventors:
GAADONAA KOTSUKUSU HENDORII
Application Number:
JP22137083A
Publication Date:
August 13, 1986
Filing Date:
November 24, 1983
Export Citation:
Assignee:
DATA GENERAL CORP
International Classes:
H03M9/00; G06F13/12; G06F13/38; G06F15/78; H04L25/45