Title:
【発明の名称】複数通信チヤネルプロトコルサポ-トシステム
Document Type and Number:
Japanese Patent JPS61500145
Kind Code:
A
Abstract:
Protocol support and message buffering circuitry is used to transmit call status, control and terminal management information bidirectionally over associated conductor pairs as signalling messages between a system processor and a phone and/or terminal served by the system and connected to each conductor pair. This information is transmitted serially in a modified HDLC format as a one bit signalling field of a multiplexed data frame. At each transmitting end, the message information is converted from a parallel to a serial format, transmitted serially as the signalling bit of successive frames, and reconverted to parallel at the receiving end. Ports terminate the system end of the conductor pairs and are mounted four to the board. Each board contains circuitry, such as registers and the like, common to the signalling message protocol support and message buffering circuitry of all four ports. The processor scans, reads and writes these common registers via the I/O bus to determine the status of each port and to exchange messages with the remote phones and terminals served by the ports. Multiplexing is used on the signalling message so that the system processor can direct a message individually to each of the plurality of station devices connected to the station end of each line. Protocol support is carried through to the processor to support the error detecting capabilities of the protocol.
Inventors:
Petsk, Stephen Richiyard
Jeepon Burton
Jeepon Burton
Application Number:
JP50372484A
Publication Date:
January 23, 1986
Filing Date:
September 24, 1984
Export Citation:
Assignee:
American Telefon and Telegraph Kampani-
International Classes:
H04L69/14; H04Q11/04; H04Q3/545; (IPC1-7): H04Q11/04; H04Q3/545; H04L13/00; H04L11/20
Attorney, Agent or Firm:
Masao Okabe