- Patent JPS6161404

Document Type and Number:

Japanese Patent JPS6161404

Kind Code:

B2

Abstract:

Two systems of synchronous logic with dissimilar maximum clocking rate requirements use a single oscillating source to derive pseudo synchronous logic related clock signals having desired mutual properties. The periods of the clock T1 and T2 form the relationship where S is a rational number and alpha is a largest denominator of T1 and T2. alpha then can be used to define a window that permits the transfer of data pulses from one of the systems to another without metastable conditions occurring in latch circuits.

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Inventors:

DONARUDO KURAIDO FUREMINGU

Application Number:

JP5870681A

Publication Date:

December 25, 1986

Filing Date:

April 20, 1981

Export Citation:

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Assignee:

INTAANASHONARU BIJINESU MASHIINZU CORP

International Classes:

G06F13/42; G06F1/12; H03K5/15; H04L7/00

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