Japanese Patent JPS616472

B2

A semiconductor memory circuit is described for use in a memory array which is capable of permitting data contained in an entire column or in an entire row to be accessed simultaneously. The invented device improves upon the traditional memory circuit, which uses a single word line and two digit lines, by adding a second word line and a third digit line coupled through the gate and drain, respectively, of a transistor device. In a preferred embodiment, all the second word lines of each column are coupled in common to form a common second word line for each column, and all the third digit lines of each row are coupled in common to form a common third digit line for each row. When a signal of a high potential is coupled to the common second word line for a particular column, all the data contained in the memory circuits of that column appears on the common third digit lines.

YASUOKA NOBUYUKI

JP14714280A

February 26, 1986

October 21, 1980

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NIPPON ELECTRIC CO

G11C11/412; G11C7/00; G11C8/16; G11C11/41; G11C11/419; H03M9/00

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