Document Type and Number:
Japanese Patent JPS6212548
Kind Code:
B2
Abstract:
A CPU implementable method for minimizing thrashing among concurrent processes demand page accessing a data base through an LRU page organized buffer pool. There is ascertained the set of pages over which there is looping access behavior for the prospectively executing concurrent processes. This parameter, as determined for each task, is passed to the storage accessing component which partitions the buffer into LRU stacks and dynamically adjusts the stack to this predicted parameter size.
Inventors:
SHOKORUNITSUKU MARIO
SATSUKO GIOANI MARIA
SATSUKO GIOANI MARIA
Application Number:
JP50285381A
Publication Date:
March 19, 1987
Filing Date:
August 18, 1981
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G06F12/12; G06F12/123