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Document Type and Number:
Japanese Patent JPS625379
Kind Code:
B2
Abstract:
A shift register circuit for converting a form of a datum with N bits comprises a shift register with a bit capacity of at least N+1 bits. Each bit of the shift register is set so as to become a predetermined logic condition by a setting means. At this time, the supply of shift pulses to the shift register is begun, so that the data in the shift register is shifted and predetermined data are input in sequence. A detecting means detects whether or not the shift register has carried out the shift operations by the predetermined times on the basis of the logical condition of the predetermined bit or bits in the shift register. When the detecting means detects that the shift operations have been carried out by the predetermined times, the supply of the shift pulses to the shift register is stopped. This shift register circuit can be used for a parallel to serial converter or a serial to parallel converter.

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Inventors:
YAMAZAWA MASAO
SOEJIMA TETSUO
Application Number:
JP4963179A
Publication Date:
February 04, 1987
Filing Date:
April 24, 1979
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03M9/00



 
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