Document Type and Number:
Japanese Patent JPS6416017
Kind Code:
U
Application Number:
JP11123887U
Publication Date:
January 26, 1989
Filing Date:
July 20, 1987
Export Citation:
International Classes:
H01B7/04; (IPC1-7): H01B7/04
Previous Patent: 基準電流調整回路、半導体装置及び基準電流調整方法
Next Patent: OUTPUT BUFFER FOR MOS SEMICONDUCTOR INTEGRATED CIRCUIT
Next Patent: OUTPUT BUFFER FOR MOS SEMICONDUCTOR INTEGRATED CIRCUIT