Document Type and Number:
Japanese Patent JPWO2023007569
Kind Code:
A1
Abstract:
The purpose of the present disclosure is to provide a switching element drive circuit that is capable of suppressing an increase in a load current flowing in a switching element in an overcurrent state even immediately after the switching element is turned on. In the present disclosure, a buffer (2) outputs a gate drive signal (S2) indicating the same logic level as that of an element control signal (S0), and an inverting buffer (3) outputs a base drive signal (S3) indicating a logic level opposite to that of the element control signal (S0). A resistor (11) is disposed between the output of the buffer (2) and a gate of an IGBT (1). An emitter of a PNP bipolar transistor (Q1) is connected to the gate of the IGBT (1), and a collector thereof is connected to a reference potential (GND). A diode (D1) is disposed between the output of the buffer (2) and a base of the PNP bipolar transistor (Q1). The output of the inverting buffer (3) is connected to the base of the PNP bipolar transistor (Q1) via a resistor (12).
Application Number:
JP2023537775A
Publication Date:
February 02, 2023
Filing Date:
July 27, 2021
Export Citation:
