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Title:
3-STATE OUTPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JPH04111528
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of transistors TRs in a control circuit without connecting TRs in an output circuit of the last stage in series by using a 2-input NAND circuit, a transfer gate, and a 2-input NOR circuit as the fundamental constitution for control of the output circuit of the last stage.

CONSTITUTION: This device consists of the 2-input NAND circuit consisting of TRs Tr1 to Tr4, the 2-input NOR circuit consisting of TRs Tr5 to Tr8, the N-type transfer gate consisting of a TR Tr9, and the output circuit of the last stage consisting of TRs Tr1O and Tr11. The terminal which is not connected to the output side of the NOR circuit out of terminals of the transfer gate is connected to the other input terminal of the HAND circuit. Thus, the number of TRs of the control circuit for the output circuit of the last stage is reduced by about 10% without giving series constitution to the output circuit of the last stage.


Inventors:
TOZAWA KAZUO
Application Number:
JP22926690A
Publication Date:
April 13, 1992
Filing Date:
August 30, 1990
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
H01L21/8238; H01L27/092; H03K19/0175; (IPC1-7): H01L27/092; H03K19/0175
Attorney, Agent or Firm:
Uchihara Shin



 
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