To detect an erroneous operation caused by signal division or noise by detecting non-coincidence with a reference count value by latching a count value at prescribed timing concerning a counter circuit for counting a clock by presetting a load value for each frame pulse.

After the prescribed load value is preset to a counter part 1 for each frame pulse FP, a clock pulse is counted for an FP term. A differentiation circuit 5, to which the frame pulse FP is supplied, impresses the latch signal to the counter part 1 when the counter part 1 counts the maximum value at the prescribed timing during the frame period, for example. Then, the latched count value of the counter part 1 is compared by a count value abnormality detection circuit 2, in which the sum of the load value and the maximum count value is stored as a reference value, and in the case of non-coincidence, a non- coincidence detect signal is outputted. Thus, the error of the count value caused by the erroneous operation of the counter circuit caused by the signal division of the clock signal supplied to the synchronous counter circuit or the generation of pulse noise is not missed.