Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ABSOLUTE VALUE SQUARE DIFFERENCE CIRCUIT
Document Type and Number:
Japanese Patent JPS613283
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of multipliers, and shorten an adjustment time and constitute an economical circuit by calculating the sums of and differences between real parts and imaginary parts of two complex number signals respectively, and calculating the sum of the products of obtained arithmetic outputs.

CONSTITUTION: The 1st adder 2-1 adds the real part aR of a complex number signal 1A to the rearl part bR of a complex number signal 1B. The 2nd adder 2-2 adds the imaginary part aI of the signal 1A to the imaginary part bI of the signal 1B. The 1st subtracter 3-1 subtracts the real part bR of the signal 1B from the real part aR of the signal 1A. The end subtracter 2-2 subtracts the imaginary part bI of the signal 1B from the imaginary part aI of the signal 1A. The output of the 1st adder 2-1 and the output of the subtracter 3-1 are multiplied by each other through the 1st multiplier and the output of the 2nd adder 2-2 and the output of the subtracter 3-1 are multiplied by each other through the 2nd multiplier. The 3rd adder 2-3 calculates the sum of those multiplication results.


Inventors:
TANAKA MOTOYASU
ONO SHINJI
Application Number:
JP12195584A
Publication Date:
January 09, 1986
Filing Date:
June 15, 1984
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F7/548; G06F7/544; G06F7/552; G06F17/16; G06G7/22; (IPC1-7): G06F7/544; G06F7/552; G06F15/347; G06G7/22
Attorney, Agent or Firm:
Masaki Yamakawa