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Patent Searching and Data


Title:
ACCESS CONTROL CIRCUIT FOR EEPROM
Document Type and Number:
Japanese Patent JPH05265842
Kind Code:
A
Abstract:

PURPOSE: To execute another processing at a CPU even during the write of an electrically erasable and programable ROM (EEPROM) and to prevent illegal access by returning an error signal in the manner of a hardware to the CPU corresponding to access during write.

CONSTITUTION: When a write start signal is received, an access control circuit 2 for an EEPROM 1 returns a reply signal from a write control part 22 to a CPU (processor) 3 and starts writing information in the EEPROM 1. At the same time, a timer 23 is started, an under-write signal is generated for a fixed time, the signal is sent to an under-write display port 24 and an address coincidence detection part 25, it is displayed that the EEPROM 1 is under writing so as to be read to the CPU 3, and the error signal in the manner of the hardware is returned corresponding to the access of the CPU 3 during the write.


Inventors:
Hideki Takeya
Application Number:
JP9235292A
Publication Date:
October 15, 1993
Filing Date:
March 19, 1992
Export Citation:
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Assignee:
Mitsubishi Electric Corporation
International Classes:
G11C16/02; G06F12/00; G06F12/16; G11C16/06; G11C17/00; (IPC1-7): G06F12/00; G06F12/16; G11C16/06
Attorney, Agent or Firm:
Hiroaki Tazawa (2 outside)