PURPOSE: To attain the uniform acquisition of a common bus by using the bus acquisition permission signal self-supported by a latch circuit to prevent the next bus request signal from entering a priority encoder.

CONSTITUTION: The bus acquisition permission signals 35 are connected to the corresponding masters respectively and at the same time supplied to a latch circuit 37 through NAND gates 36. The circuit 37 is cleared by the bus request detecting signal 38 of an 8-3 priority encoder 33 as long as the bus request signals 31 are not sent from other bus masters. While the circuit 37 latches the signals 35 when the signals 31 are received from other bus masters and then self-supported by the latched signals 39. These self-supported signals 39 are supplied to OR gates 32 to inhibit such a case where the next signals 31 of acquired bus masters are supplied to the encoder 33 through the gates 32.