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Title:
ADAPTATIVE EQUALIZER
Document Type and Number:
Japanese Patent JPH11126432
Kind Code:
A
Abstract:

To provide an adaptive equalizer in which convergence of a tap coefficient is improved while preventing degradation of follow-up characteristic of a PLL circuit.

The equalizer is made to be such primary coupling that group delay is a 0 part yei and a non-0 part y0i, group delay of the 0 part yei is used for calculation of a phase error of the PLL circuit. By constituting the device as the above, since a group delay characteristic of a filter realizing yei does not depend on a coefficient {kei} but is always 0, even if convergence of the coefficient {kei} is improved, influence for a follow-up characteristic of the PLL circuit is small. Also, as y0i is not used for calculation of a phase error of the PLL circuit, even if convergence of the coefficient {k0i} is improved, follow-up characteristic of the PLL circuit is not degraded.


Inventors:
SHIMATANI KEIJI
Application Number:
JP29092997A
Publication Date:
May 11, 1999
Filing Date:
October 23, 1997
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11B20/10; H03H17/00; H03H21/00; H03L7/06; H04B3/04; (IPC1-7): G11B20/10; H03H17/00; H03H21/00; H03L7/06; H04B3/04
Attorney, Agent or Firm:
Shunichiro Nagasawa (1 person outside)