To provide an adaptive digital filter capable of performing the high-speed processing of the operation of an update value a[n+1] of a coefficient (a) with a small-scale circuit configuration.
The adaptive digital filter 1 is provided with a digital filter 2 having the coefficient (a) set by a[n+1]=a[n]+β×e[n]×q[n]/p[n] and an NMLS computing element 3 which operates the update value a[n+1] to update the coefficient a of the digital filter 2 at each time of input of sampling data x[n]. The NMLS computing element 3 is provided with a computing element which operates a power of 2 2m exceeding the divider p[n] in an operation expression for obtaining the coefficient a, and the power of 2 2m operated by the computing element is used instead of the divider p[n] to perform operation processing of a division part β×e[n]×q[n]/2m. Since the divider of division operation is substituted with 2m, a division value is obtained by shifting each bit of a dividend by m bits, for example, by a fixed decimal point method. Therefore, a division circuit in the NMLS computing element 3 is constituted of a simple logic circuit like a bit shifter, so that the circuit configuration is simplified and high-speed processing is possible.
KITANO TOYOKAZU
| JPS6010820A | 1985-01-21 | |||
| JPS6175433A | 1986-04-17 | |||
| JPS63254525A | 1988-10-21 | |||
| JPH04283831A | 1992-10-08 | |||
| JPH06188683A | 1994-07-08 | |||
| JP2002027510A | 2002-01-25 |
Tatsuya Tanaka
Tsukasa Senba
Takashi Shiotani
Hiroshi Furusawa
Masato Tsutsui