Title:
ADAPTIVE EQUALIZER
Document Type and Number:
Japanese Patent JP3462000
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To attain light weight, miniaturization, low power consumption and low cost by conducting calculation o replical signal generation and error signal calculation or the like in a way of pipeline so as to reduce the scale of hardware required for the calculation.
SOLUTION: An object series from an object series generator 20 inputs to a line distortion estimate device 26, a line distortion signal is inputted to a replica signal generator 21 in a prescribed order, from which a replica signal is generated. Then the replica signal is inputted to a subtractor 22 in the order of generation and subtracted from a reception signal to calculate an error signal. The error signal is given to a square sum computing unit 23, in which I and Q phase signals are squared in a pipeline way succeedingly to obtain a branch metric and stored also in an error signal register 24 sequentially. Then each path metric and a branch metric to be accumulated are calculated by an adder 28 and a path metric at a current time is calculated. Then a minimum path metric is outputted to a path metric memory 29 and a maximum likelihood path estimate device 27.
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Inventors:
Mitsuo Kubo
Akira Tano
Akira Tano
Application Number:
JP9587896A
Publication Date:
October 27, 2003
Filing Date:
March 27, 1996
Export Citation:
Assignee:
Hitachi Kokusai Electric Co., Ltd.
Nippon Telegraph and Telephone Corporation
Nippon Telegraph and Telephone Corporation
International Classes:
H04L25/03; H03M13/23; H04B7/005; H04L25/08; (IPC1-7): H04B7/005; H04L25/03; H04L25/08
Domestic Patent References:
| JP7240766A | ||||
| JP884082A |
Attorney, Agent or Firm:
Manabu Otsuka
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