ADAPTIVE ERROR CORRECTION FOR NON-VOLATILE MEMORIES

Title:

ADAPTIVE ERROR CORRECTION FOR NON-VOLATILE MEMORIES

Document Type and Number:

Japanese Patent JP2014044791

Kind Code:

A

Abstract:

To provide adaptive error correction for non-volatile memories.

Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously had bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories.

Inventors:

CUNNINGHAM JEFFREY C
HORACIO P GASQUET
ROSS S SCOULLER
MARCO A CABASSI

Application Number:

JP2013173131A

Publication Date:

March 13, 2014

Filing Date:

August 23, 2013

Export Citation:

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Assignee:

FREESCALE SEMICONDUCTOR INC

International Classes:

G11C29/42; G06F12/16; G11C16/02; G11C16/06

Domestic Patent References:

JP2010123236A	2010-06-03
JP2011108306A	2011-06-02
JP2009515281A	2009-04-09
JP2010529557A	2010-08-26

Foreign References:

WO2011028235A1	2011-03-10
US20070091677A1	2007-04-26
US20070201274A1	2007-08-30
US20080307270A1	2008-12-11

Attorney, Agent or Firm:

Tadashige Ito
Tadahiko Ito
Shinsuke Onuki

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