Title:
ADAPTIVE METHOD FOR REDUCING NOISE
Document Type and Number:
Japanese Patent JP3800147
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To efficiently cancel variable cyclic noise from a main input.
SOLUTION: A variable cyclic pulse signal and a sampling clock are input to a counter means 32 in an adaptive signal processor 30, and an input cycle is counted by a sampling clock to input a count value to a timing generation means 34. XV addresses and Xk-1 addresses are sequentially generated from 0 to M respectively by a variable reading address generation means 33 and a writing address generation means 35 based on the timing pulse thereof, and input as reading and writing addresses for an accumulator 36. A signal obtained by executing a unit sample time delay 37 for the output of an adder 38 to which an error signal 2μEk multiplied by a step gain μ and data Wk read from the address Xk are input is written in the Xk-1 address. Then, an adaptive coefficient WV is read from the XV address, and input through a data interpolation means 39 to one end of an adder 9.
Inventors:
Kazuhiko Ozawa
Application Number:
JP2002230368A
Publication Date:
July 26, 2006
Filing Date:
August 07, 2002
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G11B20/24; G11B20/10; H03H21/00; (IPC1-7): G11B20/24; G11B20/10; H03H21/00
Domestic Patent References:
| JP5040485A | ||||
| JP5127679A | ||||
| JP6035487A | ||||
| JP7199962A | ||||
| JP3277009A | ||||
| JP11232803A | ||||
| JP11232802A | ||||
| JP61288613A |
Attorney, Agent or Firm:
Yoshitsuno Kakuda
Hironobu Isoyama
Hironobu Isoyama
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