PURPOSE: To execute at a high speed a reducing operation of a circuit scale by using two full adders, outputting a result of the second full adder when there is no carry in a first full adder, and outputting a result of the first full adder when there is the carry.

CONSTITUTION: The first full adder 1 of (m) bits calculates [α+β+1] which add '1' to two inputs α, β, and simultaneously, the second full adder 2 of (m) bits calculates [α+β], and when there is no carry in the first full adder 1 of (m) bits, an output of the second full adder 2 of (m) bits is selected by a selector 3 and outputted, and when there is the carry, an output of the first full adder 1 of (m) bits is selected and outputted. Accordingly, an all '1' detector is not required, and the first full adder 1 of (m) bits and the second full adder 2 of (m) bits operate simultaneously, therefore, the operation is executed at a high speed.