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Title:
ADDRESS COMPARISON STOPPING SYSTEM
Document Type and Number:
Japanese Patent JPH01273143
Kind Code:
A
Abstract:

PURPOSE: To stop the execution of a program in a prescribed address by stopping the execution of the program, in case data which has been written in advance has been read out of a spare bit circuit, when a prescribed address is inputted to a main storage circuit and the spare bit circuit and a processing is executed, based on the program which has been read out.

CONSTITUTION: A control circuit 1 writes in advance data (for instance, data '1') in the position concerned in a spare bit circuit 3 corresponding to an address for stopping the execution of a program. In this state, in case a prescribed address is set successively to a main storage address register (SAR) 5 and a program which has been read out of a main storage circuit (MS) 2 is executed, when the data which has been read out together from the spare bit circuit 3 is, for instance, '1', the execution of the program is stopped. In such a way, by utilizing the spare bit circuit 3 provided for a change against the MS 2, the execution of the program can be stopped in a designated address by a simple circuit constitution.


Inventors:
OTA TAKEO
Application Number:
JP10183988A
Publication Date:
November 01, 1989
Filing Date:
April 25, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/28; (IPC1-7): G06F11/28
Attorney, Agent or Firm:
Teiichi Ijiba (2 outside)



 
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