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Title:
ADDRESS CONVERSION SYSTEM
Document Type and Number:
Japanese Patent JPH04133153
Kind Code:
A
Abstract:

PURPOSE: To efficiently use the system bus by providing a bus converting circuit for converting an address format of a high system bus of a CPU side, discriminating a data transfer unit and a control space address, and executing an access to peripheral controller being a subordinate of a low system bus.

CONSTITUTION: A bus converting circuit 10 is provided between a low system bus 30 for containing a peripheral controller, and a high system bus 20 for connecting a CPU, a main storage device, etc. The bus 20 is that which has a control space address of 32 bits, and the bus 30 is a standard bus. The CPU constitutes an address on the but 30 to an address format allocated to a different area at every data transfer unit and sends it out. The bus converting circuit 10 discriminates the data transfer unit and the control space address on the bus 30 from the address constituted in accordance with the address format, and executes an access to the peripheral controller.


Inventors:
MASUDA ETSUO
UEMORI AKIRA
NAMIKAWA IKUO
KIMURA MINORU
Application Number:
JP25613590A
Publication Date:
May 07, 1992
Filing Date:
September 26, 1990
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
HITACHI LTD
International Classes:
G06F12/10; G06F12/08; G06F13/36; (IPC1-7): G06F12/10; G06F13/36
Attorney, Agent or Firm:
Masatoshi Isomura



 
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