Title:
ADDRESS GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP3426271
Kind Code:
B2
Abstract:
PURPOSE: To decrease a chip area by reducing the rate of the address generating circuit occupying a semiconductor memory by generating a count pulse from a count pulse generating circuit corresponding to an external input, controlling an up/down counter corresponding to that pulse and generating an offset loaded address.
CONSTITUTION: A counter load value generating circuit 33 generates the load value of a three-bit down counter 31 corresponding to signals YR and CR and the inputs of signals 3a-3d fixed to either 'H' or 'L.' Next, corresponding to signals CLK, P0-P3 and MCY, a counter control circuit 32 generates control signals NL, CI and NE of the three-bit down counter 31 and a set signal S of a latch circuit 34, the three-bit down counter 31 generates a signal CO corresponding to the load value, and a signal ASC is generated by resetting the output of the latch circuit 34.
Inventors:
Kunihiro Yamaoka
Hideki Kawai
Hideki Kawai
Application Number:
JP32665292A
Publication Date:
July 14, 2003
Filing Date:
December 07, 1992
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F5/10; G06F5/06; G06F13/38; G11C8/04; (IPC1-7): G06F5/06; G06F13/38; G11C8/04
Domestic Patent References:
| JP293825A | ||||
| JP56124935A | ||||
| JP5933687A | ||||
| JP59100616A |
Attorney, Agent or Firm:
Akio Miyai