Title:
ADDRESS PATTERN GENERATOR
Document Type and Number:
Japanese Patent JP3605150
Kind Code:
B2
Abstract:
PURPOSE: To provide an address generator capable of changing burst length of an SDRAM during testing, capable of switching an interleave mode and a sequential mode with each other during testing, and generating a column address by means of one Y-address generating part.
CONSTITUTION: An address selector 40 is provided for selectively outputting a Y-address signal (Y0-2), Z-address signal (Z0-2), and an action mode control signal (C0), and a translation memory 50 is provided for outputting a specific translation table content. A multiplexer 60 is provided for selectively outputting output (B0-2) of the translation memory 50 and the Y-address signal (Y0-2) in accordance with a burst length control signal (BS0-2). As another example, the generator may be constituted by providing a counter, a difference gate, and a multiplexer for selecting respective output signals.
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Inventors:
Toru Inagaki
Kenichi Fujisaki
Kenichi Fujisaki
Application Number:
JP22097994A
Publication Date:
December 22, 2004
Filing Date:
August 22, 1994
Export Citation:
Assignee:
Advantest Corporation
International Classes:
G01R31/3181; G06F9/34; G01R31/3183; G06F12/00; G06F12/02; G11C29/04; G11C29/10; G11C29/18; G11C29/20; G01R31/319; (IPC1-7): G01R31/3183; G11C29/00
Domestic Patent References:
| JP5188116A | ||||
| JP7041798U | ||||
| JP7262799A |
Attorney, Agent or Firm:
Taku Kusano
Minoru Inagaki
Minoru Inagaki