Title:
METHOD AND DEVICE FOR VERIFYING DESIGN BY USING EMULATION AND SIMULATION
Document Type and Number:
Japanese Patent JP3131177
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To efficiently combine simulation and emulation for logical design by providing the system with a reconstitutable device for emulating a part of logical design in verification and using a microprocessor for simulating the other design part.
SOLUTION: Each of programmable gate array(FPGA) devices 10 to be mutually connected by a programmable mutual connector 12 emulates a logical circuit part in verification as the mutual connection of components. Each of plural simulation modules 14 simulates a logical circuit part in verification and the logical circuit part can be expressed by action description. A microprocessor 16 in each simulation module 14 selectively executes a fragment of action description. Then the microprocessor 16 is released from the functions of event detection, scheduling and ordering. Consequently simulation speed is dramatically improved.
Inventors:
Stephen Pee Sample
Miku Hale Burstein
Miku Hale Burstein
Application Number:
JP32187997A
Publication Date:
January 31, 2001
Filing Date:
October 17, 1997
Export Citation:
Assignee:
QUICKTURN DESIGN SYSTEMS, INC.
International Classes:
G06F11/22; G06F11/26; G01R31/28; G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP9293002A | ||||
| JP2291980A | ||||
| JP9153077A | ||||
| JP7506685A |
Other References:
【文献】欧州特許出願公開777180(EP,A2)
【文献】1.Michael Butts,”Future Directions of Dynamically Reprogrammable Systems”,IEEE CICC,IEEE,1995年,p.487~494
【文献】2.http://support.xilinx.co.jp/prs rls/qturnDAC.htm
【文献】1.Michael Butts,”Future Directions of Dynamically Reprogrammable Systems”,IEEE CICC,IEEE,1995年,p.487~494
【文献】2.http://support.xilinx.co.jp/prs rls/qturnDAC.htm
Attorney, Agent or Firm:
Aoyama Ryo (2 outside people)