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Patent Searching and Data


Title:
AIS SIGNAL DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS6485452
Kind Code:
A
Abstract:

PURPOSE: To surely detect an AIS signal even when data error exists by receiving 0 detection/undetection information from a monitoring storage means and deciding it as the detection of an AIS signal when the number of signal lines detecting 0 in the n-line of signal lines is a specified number or below.

CONSTITUTION: A control means 2 generates a timing signal deciding a monitoring range and controls the entire operation of an AIS(Alarm Indication Signal) signal detection circuit. Monitoring storage means 11∼14 receive a timing signal from the control means 2 to monitor whether or not the signal 0 is received at every signal in the n-parallel signal in the monitoring range and stores it till the next monitoring range is started newly when it is received. A deciding means 1 receives the 0 detection/undetection information for n-set of signals from the monitoring storage means 11∼14 and decides it as the reception of the AIS signal when the number of signal lines detecting 0 is the prescribed number or below and it is outputted externally. Thus, some degree of data error is allowed to detect the AIS signal.


Inventors:
ASHI MASAHIRO
SUGANO TADAYUKI
Application Number:
JP24070787A
Publication Date:
March 30, 1989
Filing Date:
September 28, 1987
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H04L69/40; H04L13/00; H04L25/02; (IPC1-7): H04L13/00; H04L25/02
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)