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Title:
ALIGNER
Document Type and Number:
Japanese Patent JPH1154423
Kind Code:
A
Abstract:

To provide an aligner by which desired exposure can be performed under optimum conditions by minimizing the out-of-focus exposure, even when the flatness of a semiconductor wafer partially varies.

The flatness of each one-chip-size region 15A on a semiconductor wafer is measured. A virtual plane 28 is determined in each region according to the measured flatness information. When the region 15A is exposed to light in region units, a stage 16 for exposure is tilted so as to obtain an optimal angle between a normal 29 on the virtual plane 28 and an optical axis 30 of an aligner optical system.


Inventors:
KANZAKI TOYOKI
OTSUKI KUNIO
Application Number:
JP22086797A
Publication Date:
February 26, 1999
Filing Date:
July 31, 1997
Export Citation:
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Assignee:
HORIBA LTD
International Classes:
G03F7/20; G03F7/207; G03F9/00; H01L21/027; (IPC1-7): H01L21/027; G03F7/20; G03F7/207
Attorney, Agent or Firm:
Hideo Fujimoto