Title:
CISC型からRISC型命令への変換のためのアライメント並びにデコーディング
Document Type and Number:
Japanese Patent JP3547052
Kind Code:
B2
Abstract:
A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instruction bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
Inventors:
Coon bullet
Yoshiyuki Miyayama
New En Retron
One Johannes
Yoshiyuki Miyayama
New En Retron
One Johannes
Application Number:
JP51730693A
Publication Date:
July 28, 2004
Filing Date:
March 30, 1993
Export Citation:
Assignee:
Transmeta corporation
International Classes:
C10G1/00; C10G17/02; G06F9/22; G06F9/30; G06F9/318; G06F9/38; G06F15/76; (IPC1-7): G06F9/30; G06F9/38
Domestic Patent References:
| JP5197544A | ||||
| JP3201030A | ||||
| JP63192135A | ||||
| JP63163634A |
Attorney, Agent or Firm:
Ryukichi Abe
Hirukawa Masanobu
Hiroki Shirai
Norihiko Uchida
Hideo Sugai
Kenji Aoki
Hiroshi Nagisawa
Akira Yonezawa
Hirukawa Masanobu
Hiroki Shirai
Norihiko Uchida
Hideo Sugai
Kenji Aoki
Hiroshi Nagisawa
Akira Yonezawa