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Patent Searching and Data


Title:
ANALOG PHASE LOCKED LOOP
Document Type and Number:
Japanese Patent JPH06120821
Kind Code:
A
Abstract:

PURPOSE: To apparently keep the offset voltage at fixed level and to keep the stable synchronous characteristic to the temperature fluctuation by offsetting the temperature fluctuation caused in the offset voltage of an analog phase comparator PD by the temperature compensating voltage generated by a temperature compensating circuit.

CONSTITUTION: In regard to an analog PLL, the temperature compensating voltage generated by a temperature compensating circuit 7 is given to an adder 8 and added to the phase difference component PD outputted from an analog PD 4. This added voltage is given to a loop amplifier 6. The temperature compensating voltage is properly defined as the voltage that has the same value as the temperature fluctuation value of the offset voltage caused by the temperature characteristic difference between a pair of diodes of the PD 4 and has the opposite polarity to the temperature fluctuation value. Thus the offset voltage of the PD 4 is apparently kept at a fixed level when the temperature compensating voltage is added to the component PD.


Inventors:
GIDOU TAKANOBU
Application Number:
JP28712992A
Publication Date:
April 28, 1994
Filing Date:
October 02, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03L1/02; H03L7/093; (IPC1-7): H03L7/093; H03L1/02
Attorney, Agent or Firm:
Masaki Yamakawa