PURPOSE: To decrease the leakage of a clock by detecting the leakage of a clock applied to a gate in an analog switch comprising series connection of an MOSFET switch and a capacitive MOSFET to control the phase difference of the two clocks.

CONSTITUTION: If the leakage of a clock signal takes place in the analog switch comprising MOSFETs M41, M42, the same amount of the signal leakage is caused also in the analog switch comprising MOSFETs M43, M44, and the leakage is amplified by an operational amplifier OP42 and integrated by integration circuits R41, C43 and an operational amplifier OP43, the result is fed to a gate of an MOSFETM45 to change the drain-source resistance, and a clock N4 is delayed by the cooperation of a resistor R43 and a capacitor C44 to control the phase. When an output of the operational amplifier OP42 is negative, for example, an output of the operational amplifier OP43 is increased as the sample holding is repeated, the resistance value of the FETM45 is decreased, the delay of the clock to the FETs M42, M44 is increased, and the leakage error is decreased and becomes close to zero.