Title:
ANALOG-TO-DIGITAL CONVERTER MINIMIZING QUASI-STABLE STATE
Document Type and Number:
Japanese Patent JPH04261223
Kind Code:
A
Abstract:
PURPOSE: To attain the minimum semi-stable state by interposing an AND gate between each latch and an encoder. CONSTITUTION: A 3 input AND gate 30 is interposed between an L2 latch 15 and an encoder 16. Thus, the generation of an error resulted from a noise on a resistor column and/or an error resulted from the difference of propagation delay at the passage through the plural stages of a comparator can be extremely reduced. Also, more than two one hot codes(OHC) can be prevented from being transmitted to the encoder 16 by the gate 30. That is, one output of the latch 15 is connected with one gate 30, and the other output is connected with the two different gates 30 in parallel. A thermometer code input to the latch 15 is converted into the OHC output by the gate 30, and transmitted to a lead 31. Thus, the minimum semi-stable state can be realized.
Inventors:
POORU UINSHIN CHIYUN
KAARU REIMONDO HENSE
KIMU IEN NIYUEN
KAARU REIMONDO HENSE
KIMU IEN NIYUEN
Application Number:
JP40857490A
Publication Date:
September 17, 1992
Filing Date:
December 28, 1990
Export Citation:
Assignee:
IBM
International Classes:
H03M1/36; H03M1/08; (IPC1-7): H03M1/36
Domestic Patent References:
| JPH01259628A | 1989-10-17 | |||
| JPS6359111A | 1988-03-15 | |||
| JPS6286918A | 1987-04-21 | |||
| JPH01248828A | 1989-10-04 |
Attorney, Agent or Firm:
Koichi Tonmiya