To make an AD converter operate in high speed including a cyclic type composition.
In a prestage, a 1st AD converter 12 converts an input analog signal to a digital value, and extracts top 4 bits (D9 to D6). In a poststage, a 2nd AD converter 17 converts an input analog signal to a digital value, and extracts 3 bits (D6 to D4) including redundant bits of 5th, 6th from a top, 3 bits (D7 to D4) including redundant bits of 7th, 8th bits from the top, 3 bits (D4 to D2) including redundant bits of 9th, 10th bits from the top, and 3 bits (D2 to D0) including redundant bits. Thus, a number of conversion bits of the 2nd AD converter 17 of the cyclic type in the poststage is set smaller than a number of conversion bits of the 1st AD converter 12 in the prestage.
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TANI KUNIYUKI
KOBAYASHI SHIGETO
