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Title:
APPARATUS AND METHOD FOR MEASURING CONSUMED POWER IN DIGITAL SIGNAL PROCESSOR USING TRACE DATA AND SIMULATION TECHNIQUE
Document Type and Number:
Japanese Patent JP2003178106
Kind Code:
A
Abstract:

To provide a method and device for measuring the consumed power of any ventral processing unit with a program under execution.

Using a trace component, the input signal, output signal and interrupt conditions for each clock cycle are decided for measuring the consumed power of the central processing unit 21 with the program under execution. The decided input signal and output signal are applied to a simulation model 26 of a central processing system, and the condition of the central processing unit 21 at each clock cycle is decided. The simulation model 26 is used to decide the power consumption in each condition. The information about the condition progress of the central processing unit is combined with the power consumption of the central processing unit 21, and the power consumption of the central processing unit 21 is decided as a function of the program execution. Through comparison of the power consumption with that program part which is under execution, the program is adjusted so as to decrease the requisite power while the program is under execution.


Inventors:
SWOBODA GARY L
Application Number:
JP2002231352A
Publication Date:
June 27, 2003
Filing Date:
August 08, 2002
Export Citation:
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Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G01R21/133; G06F17/50; (IPC1-7): G06F17/50
Attorney, Agent or Firm:
Akira Asamura (3 outside)