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Title:
APPARATUS FOR TESTING SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2010040133
Kind Code:
A
Abstract:

To provide a semiconductor memory testing apparatus that efficiently retrieves fail chips meeting the desired conditions and displays results of testing in an easy to view way.

The semiconductor memory testing apparatus constructed to allow fail bit map display for every wafer based on fail data taken from a fail memory is provided with a section for setting a chip retrieving condition for arbitrarily setting the fail chip retrieving condition.


Inventors:
NOGAMI ATSUKO
Application Number:
JP2008203771A
Publication Date:
February 18, 2010
Filing Date:
August 07, 2008
Export Citation:
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Assignee:
YOKOGAWA ELECTRIC CORP
International Classes:
G11C29/44
Domestic Patent References:
JP2000260843A2000-09-22
JP2002170393A2002-06-14
JPH10104314A1998-04-24
JP2001267389A2001-09-28
JPH07221156A1995-08-18
JPH06275696A1994-09-30
JP2007287272A2007-11-01
JP2009135151A2009-06-18
Foreign References:
WO2004068414A12004-08-12



 
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